同步FIFO之VHDL描述4
今天准备完成同步FIFO其他模块的代码，主要包括读指针管理和产生电路，FIFO状态判断电路，以及双端口RAM的VHDL描述。先是读指针管理和产生电路：
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-- Designer : skycanny
-- Date : 2007-2-3
-- Description : read_pointer is created
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity read_pointer is
generic
(
depth : positive
);
port
(
clk : in std_logic;
rst : in std_logic;
rq : in std_logic;
empty : in std_logic;
rd_pt : out std_logic_vector(depth - 1 downto 0)
);
end entity read_pointer;
architecture RTL of read_pointer is
signal rd_pt_t : std_logic_vector(depth - 1 downto 0); -- read pointer counter
begin
process(rst, clk)
begin
if rst = '0' then
rd_pt_t <= (others => '0');
elsif clk'event and clk = '1' then
if rq = '0' and empty = '0' then
rd_pt_t <= rd_pt_t + 1;
end if;
end process;
rd_pt <= rd_pt_t;
end RTL;
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刚才想了一下，读写指针产生电路必须要对FIFO的状态进行判断，所以又对上面的代码进行了一点修改（上面的代码是修改过的），判断FIFO的状态，这一点在刚开始的时候给疏忽了，幸好刚才给发现了。同样昨天写的写指针产生电路没有判断FIFO的full状态，也要进行修改，还是在昨天的基础上修改吧，就不在这里罗嗦了，下面就是FIFO状态判断电路的VHDL描述。
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-- Designer : skycanny
-- Date : 2007-2-3
-- Description : read_pointer is created
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity judge_status is
generic
(
depth : positive
);
port
(
clk : in std_logic;
rst : in std_logic;
wr_pt : in std_logic_vector(depth - 1 downto 0);
rd_pt : in std_logic_vector(depth - 1 downto 0);
empty : out std_logic;
full : out std_logic
);
end entity judge_status;
architecture RTL of judge_status is
begin
process(rst, clk)
begin
if rst = '0 then
empty <= '1';
elsif clk'event and clk = '1' then
if wr_pt = rd_pt then
empty <= '1';
else
empty <= '0';
end if;
end if;
end process;
process(rst, clk)
begin
if rst = '0' then
full <= '0';
elsif clk 'event and clk = '1' then
if wr_pt > rd_pt then
if (rd_pt + depth) = wr_pt then
full <= '1';
else
full <= '0';
end if;
else
if (wr_pt + 1 ) = rd_pt then
full <= '1';
else
full <= '0';
end if;
end if;
end if;
end process;
end RTL;
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广告时间欢迎访问skycanny的笔记(副站) 。现在就开始双口RAM的VHDL描述吧，这个可是很重要的。下面的代码在Altera的CycloneII系列的器件上通过了后仿真。
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-- Designer : skycanny
-- Date : 2007-2-3
-- Description : This VHDL file is designed to generate a dual port ram
-- Device : Cyclone II
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dualram is
generic
(
width : positive := 16;
depth : positive := 8
);
port
(
------------------------- port a is only for writing -------------------------------
clka : in std_logic;
wr : in std_logic;
addra : in std_logic_vector(depth - 1 downto 0);
datain : in std_logic_vector(width - 1 downto 0);
------------------------------------------------------------------------------------
------------------------- port b is only for reading -------------------------------
clkb : in std_logic;
rd : in std_logic;
addrb : in std_logic_vector(depth - 1 downto 0);
dataout : out std_logic_vector(width - 1 downto 0)
------------------------------------------------------------------------------------
);
end entity dualram;
architecture Behavioral of dualram is
type ram is array(2 ** depth - 1 downto 0) of std_logic_vector(width - 1 downto 0);
signal dualram : ram;
begin
process(clka, clkb)
begin
if clka'event and clka = '1' then
if wr = '0' then
dualram(conv_integer(addra)) <= datain;
end if;
end if;
end process;
process(clkb)
begin
if clkb'event and clkb = '1' then
if rd = '0' then
dataout <= dualram(conv_integer(addrb));
end if;
end if;
end process;
end Behavioral;
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抓个后仿真的图形吧，需要testbench的投票留言。另外今天还发现前仿真的时候可以用generic传递参数，而后仿真的时候就不能用generic传递参数了，Modelsim会报错“No default binding for component at”。后来想了一下确实应该是这样的，因为后仿真的时候电路都已经布局布线完成了，还有什么参数需要generic传递呀？
今天就到这里吧，大家赶快给我投票啊，吼吼！欢迎访问skycanny的笔记(副站)。
