|
序列检测器
//file name:seridetec.v
//function: 序列检测器,检测序列为:"01101"
//利用状态机实现.
module seridetec(x,z,clk,rst);
input x,clk,rst;
output z;
reg[8:0] state;
wire z;
parameter IDLE=8'd1,
A=8'd2,
B=8'd4,
C=8'd8,
D=8'd16,
E=8'd32,
F=8'd64,
G=8'd128;
assign z=(state==D && x==1)?1:0;
always@(posedgeclk or negedge rst)
if(!rst)
begin
state<=IDLE;
end
else
casex(state)
IDLE:if(x==0)
state<=A;
else state<=IDLE;
A:if(x==1)
state<=B;
else state<=A;
B:if(x==1)
state<=C;
else state<=F;
C:if(x==0)
state<=D;
else state<=G;
D:if(x==1)
state<=E;
else state<=A;
E:if(x==1)
state<=C;
else state<=A;
F:if(x==0)
state<=A;
else state<=B;
G:if(x==0)
state<=F;
else state<=G;
default: state<=IDLE;
endcase
endmodule |
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